This invention is intended to solve certain problems involved in building layered structures incorporating high-density electronic circuitry.
U.S. Pat. Nos. 4,525,921, issued July 2, 1985, and 4,551,629, issued Nov. 5, 1985, both assigned to the assignee of this application, disclose the use of modules containing stacks of semiconductor (e.g., silicon) chips, each of which carries integrated circuitry having a large number of closely-spaced, independent electrical leads exposed at the end of the chip. The stacked chips thus provide a three-dimensional laminated structure, having on one end surface (formed by the ends of the laminations) a mosaic of separate electrical leads, whose total number is the product of the number of chips in the stack times the number of leads on each chip.
Because the numerous leads are very closely spaced, but require independent connections to external elements, such as sensors (e.g., photo-detectors), or lead-out terminals, the subsequent ability to align the leads with their individual contact elements, while avoiding any short circuits, requires that extremely tight tolerances be maintained in positioning the leads on the surface of the module. During stacking of the chips to form a unitary structure, misalignment can occur both parallel to, and perpendicular to, the planes in which the chips extend. The latter problem has been particularly difficult to solve.
In general, the purpose of the present invention is to provide a stack of chips, or other substrates, whose electrical leads are aligned within close tolerances, which in some instances may be as close as a tolerance of 0.0005 in. in the X-axis (parallel to the chip plane), and a tolerance of 0.001 in. in the Y-axis (perpendicular to the chip plane). Alignment in the X-axis is a function of the accuracy of the cutting of individual chips from the wafer. Alignment in the Y-axis is a function of the thickness of the bonding material between adjacent chips and of the thickness of each chip.